H55S2532JFR-75M Datasheet | SK Hynix

.. 256MBit MOBILE SDR SDRAMs based on 2M x 4Bank x32 I/O Specification of 256M (8Mx32bit) Mobile SDRAM Memory Cell Array - Organized as 4banks of 2,097,152 x32 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.0 / Nov. 2008 1 11256Mbit (8Mx32bit) Mobile SDR .. H55S2622JFR Series H55S2532JFR Series Document Title 4Bank x 2M x 32bits Synchronous DRAM Revision History Revision No. 0.1 0.2 1.0 Initial Draft IDD Specification updated The final version History Draft Date May 2008 May 2008 Nov. 2008 Remark Preliminary Preliminary Rev 1.0 / Nov. 2008 11256Mbit (8Mx32bit) Mobile SDR .. H55S2622JFR Series H55S2532JFR Series DESCRIPTION The Hynix H55S262(53)2JFR is suited for non-PC application which use the batteries such as PDAs, 2.5G and 3G cellular phones with internet access and multimedia capabilities, mini-notebook, hand-held PCs. The Hynix 256M Mobile SDRAM is 268,435,456-bit CMOS Mobile Synchronous DRAM(Mobile SDR), ideally suited for the main memory applications which requires large memory density and high bandwidth. It is organized as 4banks of 2,097,152 x32. Mobile SDRAM is a type of DRAM which operates in synchronization with input clock. The Hynix Mobile SDRAM latch each control signal at the rising edge of a basic input clock (CLK) and input/output data in synchronization with the input clock (CLK). The address lines are multiplexed with the Data Input/ Output signals on a multiplexed x16 Input/ Output bus. All the mands are latched in synchronization with the rising edge of CLK. The Mobile SDRAMs provides for programmable read or write Burst length of Programmable burst lengths: 1, 2, 4, 8 locations or full page. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. The...